The purpose of this application note is to demonstrate the detectability of electromigration in a semiconductor sample with the high resolution nanoXCT™. The test structure before and after the test was imaged on the tool and then reconstructed into a 3D volume as shown in the movie clips. The test structure is a 75 micron thick Si chip with Cu interconnects.
The sample is courtesy of Dave Vallet of IBM Corporation.
Reconstructed 3D volume before test
Reconstructed 3D volume after test
This set of images from the nanoXCT shows the test structure after a current was applied. The Via is clearly missing.
Virtual Delayering before test
Virtual Delayering after test
